1. Field of the Invention
The embodiments of the present invention relate to the field of display, and particularly to a gate driving circuit, a display device, and a driving method.
2. Description of the Related Art
At present, a thin film transistor liquid crystal display (TFT-LCD) has become a mainstream display. The liquid crystal display has undergone a qualitative leap due to application of the gate-driver on array (GOA) technology in the liquid crystal display. Manufacturing steps and costs can be reduced by use of the GOA technology in which gate driver integrated circuits are manufactured directly on an array substrate in a liquid crystal display panel, instead of driver chips manufactured by externally connected chip. However, in an existing dual-gate design of the liquid crystal display panel to which the GOA technology is applied, gate driving can achieve only a positive Z scanning, thereby sufficiently charging one column of pixel units in the liquid crystal display panel and insufficiently charging another column of pixel units in the liquid crystal display panel. As a result, phenomena, such as poor vertical lines (V-lines), tend to occur. This will be described as below by an example in which a dual-gate liquid crystal display panel is driven in 1+2-dot inversion as shown in FIG. 1.
FIG. 1 shows a circuit diagram of an array substrate of a liquid crystal display panel in the prior art. As shown in FIG. 1, the array substrate comprises a plurality of data lines 1, a plurality of gate lines 2 (Gate 1-Gate 8), and a plurality of pixel units defined by the plurality of data lines and the plurality of gate lines. The plurality of pixel units form an array of pixel units. Each pixel unit is connected to one gate line and one data line through one thin film transistor (TFT). The gate line is connected to a gate of the thin film transistor, and the data line is connected to a source of the thin film transistor. Among each row of pixel units, the pixel units in odd-numbered columns are connected to the same gate line, the pixel units in the even-numbered columns are connected to another gate line, and the pixel units in two adjacent columns are connected to the same data line. The plurality of data lines 1 are driven by a data driving circuit, and receive data signals outputted by the data driving circuit. The plurality of gate lines 2 are connected to a gate driving circuit, and the gate driving circuit comprises a plurality of shift register units SR1-SR8. The plurality of shift register units are sequentially turned on and off during one frame scan and pulse signals generated by the plurality of shift register units SR1-SR8 after being turned on are outputted to the plurality of gate lines 2, respectively. After the frame scan begins, in a first scanning period, a first shift register unit SR1 is turned on and outputs a pulse signal to a first gate line Gate 1 so that the thin film transistors of the pixel units in the odd-numbered columns of a first row are turned on, the corresponding data lines receive data signals to charge the pixel units in the odd-numbered columns of the first row, and corresponding data are stored; and in a second scanning period, the first shift register unit SR1 is turned off, and a second shift register unit SR2 is turned on and outputs a pulse signal to a second gate line Gate 2, and at this time, the thin film transistors of the pixel units in the even-numbered columns of the first row are turned on, and the corresponding data lines charge the pixel units in the even-numbered columns of the first row. Then, a third shift register unit, a fourth shift register unit, and the like are sequentially turned on and output pulse signals to charge the corresponding pixel units in cooperation with the corresponding data lines. A polarity of data outputted to the data lines in each scanning period is inversed and polarities of data in the two adjacent data lines within each scanning period are also opposite to each other. Therefore, if a polarity of a data signal received by the pixel units in the odd-numbered columns of the first row is positive in the first scanning period, a polarity of a data signal received by the pixel units in the even-numbered columns of the first row will be changed from a positive polarity to a negative polarity in the second scanning period. In consideration of loads of the data lines, a charging time and a charge ratio of the pixel units in the even-numbered columns of the first row will be affected. The pixel units in the even-numbered columns of the first row are insufficiently charged compared with the pixel units in the odd-numbered columns of the first row. In a third scanning period, a third shift register SR3 outputs a pulse signal to a third gate line Gate 3 so that the pixel units in the odd-numbered columns of a second row begin to be charged. At this time, since a polarity of data signals in the data lines has been negative, a charging time and a charge ratio of the pixel units in the odd-numbered columns of the second row are relatively sufficient. However, the pixel units in the even-numbered columns of the second row will also be insufficiently charged. In conclusion, when the 1+2-dot inversion is performed, in the liquid crystal display panel based on the above configuration and inversion manner, the pixel units in the odd-numbered columns will be always charged more sufficiently than the pixel units in the even-numbered columns. When a difference between the charge ratios of the pixel units in the odd-numbered columns and the pixel units in the even-numbered columns is great, a displaying effect will be adversely affected. In other words, poor vertical lines are generated.
Therefore, when a product is designed, it is necessary to change the configuration and driving manner of the array substrate in order to avoid the difference between the charge ratios of the pixel units in the odd-numbered columns and the pixel units in the even-numbered columns, to alleviate the poor vertical lines.